Use of band edge gate metals as source drain contacts

ABSTRACT

A method includes providing a semiconductor substrate having intentionally doped surface regions, the intentionally doped surface regions corresponding to locations of a source and a drain of a transistor; depositing a layer a band edge gate metal onto a gate insulator layer in a gate region of the transistor while simultaneously depositing the band edge gate metal onto the surface of the semiconductor substrate to be in contact with the intentionally doped surface regions; and depositing a layer of contact metal over the band edge gate metal in the gate region and in the locations of the source and the drain. The band edge gate metal in the source/drain regions reduces a Schottky barrier height of source/drain contacts of the transistor and serves to reduce contact resistance. A transistor fabricated in accordance with the method is also described.

TECHNICAL FIELD

The exemplary embodiments of this invention relate generally totransistor devices and, more specifically, relate to complementary metaloxide semiconductor (CMOS) transistor devices and to the formation ofsource/drain (S/D) contacts for such devices.

BACKGROUND

Contact resistance has become a dominating factor and consideration astransistor devices such as field effect transistor (FET) devices arescaled to smaller dimensions. There is a need to provide a process and astructure to reduce contact resistance (S/D contact resistance) that arecompatible with existing processes and that are also cost effective.

SUMMARY

In a first aspect thereof the exemplary embodiments of this inventionprovide a method to fabricate a structure. The method comprisesproviding a semiconductor substrate having intentionally doped surfaceregions, the intentionally doped surface regions corresponding tolocations of a source and a drain of a transistor; depositing a layer aband edge gate metal onto a gate insulator layer in a gate region of thetransistor while simultaneously depositing the band edge gate metal ontothe surface of the semiconductor substrate to be in contact with theintentionally doped surface regions; and depositing a layer of contactmetal over the band edge gate metal in the gate region and in thelocations of the source and the drain.

In another aspect thereof the exemplary embodiments of this inventionprovide a method to reduce a Schottky barrier height of source/draincontacts of a field effect transistor. The method comprises forming agate stack comprising a gate insulator layer that overlies a surface ofa semiconductor substrate; further forming the gate stack by depositingband edge gate metal on the gate insulator layer, while also depositingthe band edge gate metal directly onto the surface of the semiconductorsubstrate at locations of the source/drain contacts; and further formingthe gate stack by depositing contact metal over the band edge gate metalto form a gate contact and source/drain contacts.

In a still further aspect thereof the exemplary embodiments of thisinvention provide a device that comprises a gate stack formed over achannel in a semiconductor substrate. The gate stack comprises a layerof gate insulator material, a layer of gate metal overlying the layer ofgate insulator material, and a layer of contact metal overlying thelayer band edge gate metal. The device further comprises source anddrain contacts adjacent to the channel. The source and drain contactseach comprise a layer of the gate metal that overlies and is in directelectrical contact with a doped region of the semiconductor substrate,and a layer of contact metal that overlies the layer of gate metal.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIGS. 1A-1G, collectively referred to as FIG. 1, illustrate a processflow suitable for fabricating a transistor in accordance withembodiments of this invention, where

FIG. 1A shows a partially fabricated preliminary structure for an nFET(left side of FIG. 1A) and a pFET (right side of FIG. 1A);

FIG. 1B shows the structure of FIG. 1A after poly exposure, a CMP andpoly removal;

FIG. 1C shows the structure of FIG. 1B after a mask is appliedeverywhere but where a CA will be formed and a reactive ion etch isperformed to define the CA;

FIG. 1D shows the structure of FIG. 1C after the CA is masked and a gatedielectric layer is applied to the inner surfaces of openings left afterdummy gate removal;

FIG. 1E shows the structure of FIG. 1D after band edge (BE) gate metaldeposition;

FIG. 1F shows the structure of FIG. 1E after a blanket deposition of CAmetal; and

FIG. 1G shows the structure of FIG. 1F after removal of the CA metal andthe BE metal from the field.

FIGS. 2A-2D, collectively referred to as FIG. 2, illustrate anotherprocess flow suitable for fabricating a transistor in accordance withembodiments of this invention, where

FIG. 2A shows a partially fabricated preliminary structure for an nFET(left side of FIG. 2A) and a pFET (right side of FIG. 2A), where in thisembodiment a gate dielectric layer (e.g., a high-k layer) is disposedbeneath the dummy gate plug;

FIG. 2B shows the structure of FIG. 2A after poly exposure, a CMP andpoly removal;

FIG. 2C shows the structure of FIG. 2B after a mask is appliedeverywhere but where a CA will be formed and a reactive ion etch isperformed to define the CA; and

FIG. 2D shows the structure of FIG. 2C after band edge (BE) gate metaldeposition.

DETAILED DESCRIPTION

In accordance with an aspect of the exemplary embodiments of thisinvention gate metals are used as S/D contacts. The gate metaldeposition can be by physical vapor deposition (PVD), chemical vapordeposition (CVD) or atomic layer deposition (ALD), as non-limitingexamples of gate metal deposition processes. For an n-type FET (nFET)band edge (BE) gate metals include TiAl, TiAlN and TiN/Al/TiN as severalnon-limiting examples. For a p-type FET (pFET) the BE gate metalsinclude thicker TiN, Re, Pt (and their carbides and nitrides) as severalnon-limiting examples.

The exemplary embodiments of this invention beneficially provide a BEgate metal as a S/D contact to reduce metal/Si contact resistance. Bythe use of these embodiments the need to provide a silicide can beeliminated. In addition there is a simplified process flow forfabricating metal contacts to the gate and the S/D, and a metal fillstep can be simultaneously performed for the gate and the S/D.

The concept of a BE metal is conventionally referred to one of theconduction band edge (NMOS) or the valence band edge (PMOS) of theconstituent semiconductor material. A goal is to reduce or minimize theSchottky barrier height, i.e., the difference between the metalworkfunction and the semiconductor (e.g., Si) electron affinity.

It can be noted that the eWF (effective workfunction) on different gatedielectrics (for the gate) or directly on the Si is not the same as thevacuum WF. This is generally explained by the Fermi level pinning model.Different interfaces can have different pinning factors such that theeWF could vary on different dielectrics. However, there is still acorrelation between the vacuum WF and the eWF: a higher WF metalexhibits a relatively higher eWF.

As considered herein a band edge gate metal (with the band edge eWF onhigh K) may no longer have a band edge eWF on the S/D depending on thepinning factor difference, but can still have an eWF that is closer tothe band edge as compared to other metal choices.

For Silicon the conduction band edge Ec: 4.05 eV and the valence bandedge Ev: 5.17 eV. The workfunctions for various metals are wellcharacterized. Reference can be made, for example, to pages 18 and 19 of“Work Functions of the Transition Metals and Metal Silicides”, TimothyJ. Drummond, Sandia National Laboratories, 1999 (SAN099-0391J).

In accordance with the embodiments of this invention, for a FET having agate stack the use of the BE metal as a gate contact results in areduction in the threshold voltage (Vt) of the FET. By applying the gatestack BE metal(s) to the S/D contacts the Schottky barrier height isreduced and current can more readily flow between the semiconductormaterial and the contact metal, which is manifested as a reduction inS/D resistance.

The presence of the BE gate metal on the S/D also beneficially impliesthat there is no need to form silicide. Silicide is conventionally usedto reduce the interface contact resistance and to function as anadhesion of the CA metal to the substrate. In state-of-the-art FETdevices, Nickel or Nickel-alloy silicides are typically used. It isknown that the use of silicides can cause a yield loss due to metaldiffusion into the substrate at typical processing temperatures (e.g.,of about 300° C.) for silicide formation, especially through defects insubstrates. The BE metals employed for fabricating the S/D contacts inaccordance with the embodiments of this invention exhibit limited metaldiffusion with no need of thermal treatment for silicide formation,thereby improving the yield.

The exemplary and non-limiting embodiments of this invention aredescribed with reference to the process flow depicted in FIGS. 1A-1G,collectively referred to as FIG. 1. In general, FIG. 1 presents anenlarged cross-sectional view of a substrate 10 having various layersdisposed over a major surface thereof. The various layer thicknesses arenot drawn to scale.

FIG. 1A shows a partially fabricated preliminary structure for an nFET(left side of FIG. 1A) and a pFET (right side of FIG. 1A). Thestructures include a substrate 10, such as a Si substrate, or a Gesubstrate, or a SiGe substrate, or a substrate formed of a Group III-Vmaterial (e.g., GaAs or an alloy thereof). A Si substrate will beassumed for explaining the process flow, although it should beappreciated that the Si substrate 10 is a non-limiting example of asuitable substrate. The substrate 10 could be a bulk substrate or asilicon on insulator (SOI) substrate. In the case of an SOI substrate 10there will be an underlying layer of buried oxide (BOX), not shown.While depicted on two separate substrates in FIG. 1, it should beappreciated that the nFETs and the pFETs can be formed on the samesubstrate 10, and this will also be assumed in the ensuing discussion.Note that portions of two adjacent transistors (T1 and T2) are shownwith, as a non-limiting example, a common Source or a common Drain (S/D)intentionally doped region 12 having associated extensions 14A, 14B. Forthe nFET the S/D region 12 can be made by an n+ implant (e.g., an Asimplant) while for the pFET the 12 the S/D region 12 can be made by a p+implant (e.g., a B implant). The implant dopant species concentrationmay be in a range of about, for example, 1×10²⁰ to about 4×10²⁰atoms/cm³. Also shown are two dummy gate structures 16A, 16B havingspacers 18A, 18B and an interlayer dielectric (ILD) layer 20. Thematerial of the dummy gate structures 16A, 16B may be amorphous Si or anitride or any suitable sacrificial material, the spacers 18A, 18B maybe any suitable spacer material such as a nitride (e.g., SiN), and theILD 20 can be any suitable dielectric (oxide, such as SiO₂) material.The width of the dummy gates 16A, 16B defines the channel length of theresultant FETs and can be in a range of about, for example, 15 nm toabout 35 nm, or more preferably about 20 nm to about 25 nm, and theheight can be in a range of about 30 nm to about 50 nm. The spacingbetween the dummy gates 16A, 16B will typically be larger and may be ina range of about 30 nm to about 40 nm and will define at least in partthe width of the Source or Drain contact area (CA) which can havesimilar dimensions to the gate dimensions. If one assumes that the S/Dregion 12 is, for example, a Source, then it is assumed that a Drainregion (and extensions) is present (not shown) on the opposite sides ofthe dummy gates 16A, 16B and at least partially underlies the associatedleft-most spacer 18A and right-most spacer 18B. The processing describedbelow applies equally to the Source and the Drain CAs.

FIG. 1B shows the structure of FIG. 1A after poly exposure, achemical-mechanical polish (CMP) and poly removal. At this point thematerial of the dummy gates 16A, 16B has been removed and the topsurface of the ILD 20 has been planarized to the top of the spacers 18A,18B.

FIG. 1C shows the structure of FIG. 1B after a mask is appliedeverywhere but where the CA will be formed, and a reactive ion etch(RIE) is performed to remove the ILD 20 within the CA to expose withinan opening 22 the underlying surface of the substrate 10 in the S/Dregion 12. The RIE chemistry is selected depending on the material ofthe ILD 20. Note that FIG. 1C shows the opening 22 as having slopingsidewalls. In other embodiments the sidewalls of the opening 22 can besubstantially vertical, or the ILD material between the opposed spacers18B, 18A can be removed entirely. The mask is also removed.

FIG. 1D shows the structure of FIG. 1C after the CA is masked and a gatedielectric layer 24 is applied to the inner surfaces of the openingsleft after the material of the dummy gates 16A, 16B was removed in theprocess step of FIG. 1B. The gate dielectric layer 24 can be anysuitable dielectric material that will not be affected by subsequentprocessing steps. One particularly suitable material is a highdielectric constant (high-k) material comprising a dielectric metaloxide having a dielectric constant that is greater than the dielectricconstant of silicon nitride of 7.5. The high-k dielectric layer 24 maybe formed by methods well known in the art including, for example, CVDand ALD. The dielectric metal oxide comprises a metal and oxygen, andoptionally nitrogen and/or silicon. Exemplary high-k dielectricmaterials include HfO₂, ZrO₂, La₂O₃, Al₂O₃, TiO₂, SrTiO₃, LaAlO₃, Y₂O₃,HfO_(x)N_(y), ZrO_(x)N_(y), La₂O_(x)N_(y), Al₂O_(x)N_(y), TiO_(x)N_(y),SrTiO_(x)N_(y), LaAlO_(x)N_(y), Y₂O_(x)N_(y), a silicate thereof, and analloy thereof. Each value of x is independently from 0.5 to 3 and eachvalue of y is independently from 0 to 2. The thickness of the high-kdielectric layer 24 may be from about 1 nm to about 10 nm, with about 5nm being one suitable value. The mask over the CA is then removed.

FIG. 1E shows the structure of FIG. 1D after BE gate metal deposition.In this process step the pFET is masked and nFET n-BE metal 26A isdeposited. The mask is then removed from the pFET, the nFET is masked,and pFET p-BE metal 26B is deposited. The mask is then removed from thenFET. Of course, the process flow could be reversed to deposit the p-BEmetal 26B first. The BE gate metal is deposited directly upon the high-kdielectric layer 24 in the gate regions, and deposited in the CA so thatthe exposed surface of the substrate 10 and the implanted S/D region 12therein is directly contacted by the BE gate metal layer 26A, 26B. TheBE gate metal 26 can have an exemplary thickness of up to about 20 nm,although a thickness of less than about 10 nm can be preferred. The BEmetal 26 can be deposited, for example, by CVD, physical vapordeposition (PVD), or atomic layer deposition (ALD). Suitable andnon-limiting nFET band edge metal 26A choices can be: Al, Ti, Er, Yb, Taand their alloys, carbides, and nitrides. Suitable and non-limiting pFETband edge metal 26B choices can be: Pt, Ir, Pd, Rh, Co, Ni, Ru, Re, andtheir alloys, carbides and nitrides.

FIG. 1F shows the structure of FIG. 1E after a blanket deposition of CAmetal 28. Any suitable contact metal can be employed such as, forexample, Al, W or Cu, and the CA metal 28 can be deposited by anyconventional process, including for example sputtering and CVD.

FIG. 1G shows the structure of FIG. 1F after removal of the CA metal 28and the BE metal 26 from the field dielectrics. A CMP can be performedto planarize the surface.

The end result is that the CA is provided with a dual metal damascenecomprising the layer of BE metal 26 in direct contact with thesemiconductor substrate 10, and the Source or Drain implant region 12,and the overlying layer of CA metal 28. The layer of BE metal 26 in theCA in each type of transistor (nFET or pFET) is identical to the BEmetal in the adjacent gate stack and can be deposited in the sameprocess operation. The presence of the layer of BE metal 26 in the CA,in contact with the underlying semiconductor material of the S/D,reduces the Schottky barrier height and thus beneficially reduces S/Dresistance. The disclosed processing beneficially eliminates the need toform a silicide.

It can be noted that the exemplary embodiments disclosed above assumethe same BE gate metal in the gate stack and in the S/D contacts,however they do not have to be the same.

It is to be understood that the processes described by FIGS. 1A-1G arefor illustration purposes. The processes to achieve band edge metal inthe gate stack and S/D contacts can be different.

For example, reference can be made to FIG. 2 for showing a non-limitingexample of an alternative process flow using, for example, a gate-firstprocess. Structures that are found also in the embodiment of FIG. 1 arelabeled accordingly.

FIG. 2A is analogous to FIG. 1A and shows a partially fabricatedpreliminary structure for an nFET (left side) and a pFET (right side).The structure includes the substrate 10, such as a Si substrate, andshows portions of two adjacent transistors (T1 and T2). The commonSource or common Drain (S/D) intentionally doped region 12 has theassociated extensions 14A, 14B. For the nFET the S/D region 12 can bemade by an n+ implant (e.g., an As implant) while for the pFET the 12the S/D region 12 can be made by a p+ implant (e.g., a B implant). Theimplant dopant species concentration may be in the range of about, forexample, 1×10²⁰ to about 4×10²⁰ atoms/cm³. Also shown are the two dummygate structures 16A, 16B having spacers 18A, 18B and an interlayerdielectric (ILD) layer 20. The material of the dummy gate structures16A, 16B may be amorphous Si or a nitride or any suitable sacrificialmaterial, the spacers 18A, 18B may be any suitable spacer material suchas a nitride (e.g., SiN), and the ILD 20 can be any suitable dielectric(oxide, such as SiO₂) material. In general the various dopants andranges of thicknesses, dimensions, dopant concentrations can be the sameas described above for FIG. 1A.

However, in this embodiment the layer of gate dielectric layer 24 hasbeen applied to the substrate 10 prior to the formation of the two dummygate structures 16A, 16B. The gate dielectric layer 24 can be anysuitable dielectric material that will not be affected by subsequentprocessing steps, and can comprise a layer of high-k material asdiscussed above. The thickness of the high-k dielectric layer 24 may befrom about 1 nm to about 10 nm, with about 5 nm being one suitablevalue.

FIG. 2B shows the structure of FIG. 2A after poly exposure, achemical-mechanical polish (CMP) and poly removal. At this point thematerial of the dummy gates 16A, 16B has been removed and the topsurface of the ILD 20 has been planarized to the top of the spacers 18A,18B. In this embodiment the removal of the dummy gates 16A, 16B exposesthe surface of the underlying gate dielectric layer 24.

FIG. 2C shows the structure of FIG. 2B after a mask is appliedeverywhere but where the CA will be formed, and a reactive ion etch(RIE) is performed to remove the ILD 20 within the CA to expose withinan opening 22 the underlying surface of the substrate 10 in the S/Dregion 12. The RIE chemistry is selected depending on the material ofthe ILD 20. FIG. 2C shows the opening 22 as having sloping sidewalls,although in other embodiments the sidewalls of the opening 22 can besubstantially vertical, or the ILD material between the opposed spacers18B, 18A can be removed entirely. The mask is also removed.

FIG. 2D shows the structure of FIG. 2C after BE gate metal deposition.In this process step the pFET is masked and nFET n-BE metal 26A isdeposited. The mask is then removed from the pFET, the nFET is masked,and pFET p-BE metal 26B is deposited. The mask is then removed from thenFET. As in the embodiment of FIG. 1E, the process flow could bereversed to deposit the p-BE metal 26B first. The BE gate metal isdeposited directly upon the high-k dielectric layer 24 at the bottom ofthe gate regions, and deposited in the CA so that the exposed surface ofthe substrate 10 and the implanted S/D region 12 therein is directlycontacted by the BE gate metal layer 26A, 26B. The BE gate metal 26 canhave an exemplary thickness of up to about 20 nm, although a thicknessof less than about 10 nm can be preferred. The BE metal 26 can bedeposited, for example, by CVD, physical vapor deposition (PVD), oratomic layer deposition (ALD). Suitable and non-limiting nFET band edgemetal 26A choices can be: Al, Ti, Er, Yb, Ta and their alloys, carbides,and nitrides. Suitable and non-limiting pFET band edge metal 26B choicescan be: Pt, Ir, Pd, Rh, Co, Ni, Ru, Re, and their alloys, carbides andnitrides.

Processing then continues as described above with respect to FIG. 1F andFIG. 1G to perform the blanket deposition of the CA metal 28, theremoval of the CA metal 28 and the BE metal 26 from the fielddielectrics, and a CMP operation to planarize the surface.

It is to be understood that although the exemplary embodiments discussedabove with reference to FIGS. 1A-1G and FIGS. 2A-2D are described withregard to planar devices, the processes described herein may be used oncommon variants of FET devices including, e.g., FET devices withmulti-fingered FIN and/or gate structures, FET devices of varying gatewidth and length, as well as ring oscillator devices. Moreover, thetransistor device can be connected to metalized pads or other devices byconventional ultra-large-scale integration (ULSI) metalization andlithographic techniques.

It is to be understood that in addition to fabricating transistor devicecontacts as discussed above, further aspects of the present inventioninclude methods to form contacts for other devices or otherwiseconstructing integrated circuits with various analog and digitalcircuitry. In particular, integrated circuit dies can be fabricated withvarious devices such as a field-effect transistors, bipolar transistors,metal-oxide-semiconductor transistors, diodes, resistors, capacitors,inductors, etc., having contacts that are formed using methods asdescribed herein. An integrated circuit in accordance with the presentinvention can be employed in applications, hardware, and/or electronicsystems. Suitable hardware and systems in which such integrated circuitscan be incorporated include, but are not limited to, personal computers,communication networks, electronic commerce systems, portablecommunications devices (e.g., cell phones), solid-state media storagedevices, functional circuitry, etc. Systems and hardware incorporatingsuch integrated circuits are considered part of this invention. Giventhe teachings of the exemplary embodiments of the invention providedherein, one of ordinary skill in the art will be able to contemplateother implementations and applications of the techniques of theinvention.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural foams as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theembodiments were chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the concepts of thisinvention for various embodiments with various modifications as aresuited to the particular use contemplated.

As such, various modifications and adaptations may become apparent tothose skilled in the relevant arts in view of the foregoing description,when read in conjunction with the accompanying drawings and the appendedclaims As but some examples, the use of other similar or equivalentsemiconductor fabrication processes, including material depositionprocesses and material removal processes may be used by those skilled inthe art. Further, the exemplary embodiments are not intended to belimited to only those materials, metals, insulators, dopants, dopantconcentrations, layer thicknesses and the like that were specificallydisclosed above. Any and all such and similar modifications of theteachings of this invention will still fall within the scope of thisinvention.

1. A method to fabricate a structure, comprising: providing asemiconductor substrate having intentionally doped surface regions, theintentionally doped surface regions corresponding to locations of asource and a drain of a transistor; depositing a layer of a band edgegate metal directly onto a gate insulator layer in a gate region of thetransistor while simultaneously depositing the band edge gate metaldirectly onto the surface of the semiconductor substrate to be incontact with the intentionally doped surface regions; and depositing alayer of contact metal directly onto the layer of band edge gate metalin the gate region and directly onto the band edge gate metal depositedin the locations of the source and the drain.
 2. The method of claim 1,where the transistor is a p-type field effect transistor, where theintentionally doped surface regions are doped with a p-type dopant, andwhere the band edge gate metal is comprised of at least one of Pt, Ir,Pd, Rh, Co, Ni, Ru, Re, and heir alloys, carbides, and nitrides.
 3. Themethod of claim 1, where the transistor is an n-type field effecttransistor, where the intentionally doped surface regions are doped withan n-type dopant, and where the band edge gate metal is comprised of atleast one of Al, Ti, Er, Yb, Ta, and their alloys, carbides, andnitrides.
 4. The method of claim 1, where the gate insulator layer iscomprised of a high dielectric constant gate insulator material.
 5. Themethod of claim 1, where the gate region is formed by a replacement gateprocess that removes a dummy gate material leaving a gate opening in adielectric material to expose an underlying surface of the substrate,further comprising forming openings in the dielectric material atlocations of the source and the drain, masking the openings in thedielectric material at the locations of the source and the drain;depositing gate insulator material into the gate opening whilepreventing with the mask the deposition of the gate insulator materialinto the openings in the dielectric material at the locations of thesource and the drain; removing the mask, depositing the band edge gatemetal directly onto the gate insulator material in the gate opening andinto the openings in the dielectric material at the locations of thesource and the drain; and depositing the layer of contact metal over theband edge gate metal.
 6. The method of claim 5, further comprisingremoving excess band edge gate metal and contact metal and planarizing atop surface of the structure.
 7. The method of claim 1, where the gateregion is formed by a gate-first process that removes a dummy gatematerial forming a gate opening that exposes an underlying surface ofthe gate insulator layer within the gate opening, further comprisingdepositing the band edge gate metal directly onto the gate insulatorlayer in the gate opening and into openings in the dielectric materialat the locations of the source and the drain; and depositing the layerof contact metal over the band edge gate metal.
 8. A method to reduce aSchottky barrier height of source/drain contacts of a field effecttransistor, comprising: forming a gate stack comprising a gate insulatorlayer that overlies a surface of a semiconductor substrate; furtherforming the gate stack by depositing band edge gate metal directly ontothe gate insulator layer, while also depositing the band edge gate metaldirectly onto the surface of the semiconductor substrate at locations ofthe source/drain contacts; and further forming the gate stack bydepositing contact metal directly onto the deposited band edge gatemetal to form a gate contact and source/drain contacts.
 9. The method ofclaim 8, where depositing the band edge gate metal on the gate insulatorlayer and also onto the surface of the semiconductor substratesimultaneously deposits the same band edge gate metal on the gateinsulator layer and also onto the surface of the semiconductorsubstrate.
 10. The method of claim 8, where depositing the contact metalis performed by blanket depositing the contact metal over the band edgemetal.
 11. The method of claim 8, where the field effect transistor is ap-type field effect transistor, where a surface region of thesemiconductor substrate at the locations of the source/drain contacts isdoped with a p-type dopant, and where the band edge gate metal iscomprised of at least one of Pt, Ir, Pd, Rh, Co. Ni, Ru, Re, and theiralloys, carbides, and nitrides.
 12. The method of claim 8, where thefield effect transistor is an n-type field effect transistor, where asurface region of the semiconductor substrate at the locations of thesource/drain contacts is doped with an n-type dopant, and where the bandedge gate metal is comprised of at least one of Al, Ti, Er, Yb, Ta, andtheir alloys, carbides, and nitrides.
 13. The method of claim 8, wherethe gate insulator layer is comprised of a high dielectric constant gateinsulator material.
 14. The method of claim , where forming the gatestack comprises a replacement gate process that removes a dummy gatematerial leaving a gate opening in a dielectric material, and where thegate insulator layer is deposited in the gate opening subsequent toremoving the dummy gate material.
 15. The method of claim 8, whereforming the gate stack comprises a replacement gate process that removesa dummy gate material leaving a gate opening in a dielectric material,and where the gate insulator layer is deposited prior to deposition ofthe dummy gate material and is exposed within the gate openingsubsequent to removing the dummy gate material. 16.-20. (canceled) 21.The method of claim 1, where depositing the layer of band edge gatemetal also deposits the layer of band edge gate metal upon sidewalls ofopenings formed in a layer of dielectric material at the locations ofthe source and drain of the transistor.
 22. The method of claim 1, wheredepositing the layer of band edge gate metal also deposits the layer ofband edge gate metal upon sidewalls of an opening formed in the gateregion.
 23. The method of claim 8, where depositing the layer of bandedge gate metal also deposits the layer of band edge gate metal uponsidewalls of openings formed in a layer of dielectric material at thelocations of the source/drain contacts.
 24. The method of claim 8, wheredepositing the layer of band edge gate metal also deposits the layer ofband edge gate metal upon sidewalls of an opening formed at a locationof the gate stack.